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R8C/24 Group, R8C/25 Group
SINGLE-CHIP 16-BIT CMOS MCU
REJ03B0117-0300 Rev.3.00 Feb 29, 2008
1.
Overview
These MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the R8C/Tiny Series CPU core, and are packaged in a 52-pin molded-plastic LQFP or a 64-pin molded-plastic FLGA. It implements sophisticated instructions for a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. Furthermore, the R8C/25 Group has on-chip data flash (1 KB x 2 blocks). The difference between the R8C/24 Group and R8C/25 Group is only the presence or absence of data flash. Their peripheral functions are the same.
1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer products, etc.
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 1 of 51
R8C/24 Group, R8C/25 Group
1. Overview
1.2
Performance Overview
Table 1.1 outlines the Functions and Specifications for R8C/24 Group and Table 1.2 outlines the Functions and Specifications for R8C/25 Group. Table 1.1 Functions and Specifications for R8C/24 Group Item Specification CPU Number of fundamental 89 instructions instructions Minimum instruction execution 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) time 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) Operating mode Single-chip Address space 1 Mbyte Memory capacity Refer to Table 1.3 Product Information for R8C/24 Group Peripheral Ports I/O ports: 41 pins, Input port: 3 pins Functions LED drive ports I/O ports: 8 pins Timers Timer RA: 8 bits x 1 channel Timer RB: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer RD: 16 bits x 2 channels (Input capture and output compare circuits) Timer RE: With real-time clock and compare match function Serial interfaces 2 channels (UART0, UART1) Clock synchronous serial I/O, UART Clock synchronous serial 1 channel interface I2C bus Interface(1) Clock synchronous serial I/O with chip select LIN module Hardware LIN: 1 channel (timer RA, UART0) A/D converter 10-bit A/D converter: 1 circuit, 12 channels Watchdog timer 15 bits x 1 channel (with prescaler) Reset start selectable Interrupts Internal: 11 sources, External: 5 sources, Software: 4 sources, Priority levels: 7 levels Clock Clock generation 3 circuits circuits * XIN clock generation circuit (with on-chip feedback resistor) * On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has a frequency adjustment function * XCIN clock generation circuit (32 kHz) Real-time clock (timer RE) Oscillation stop detection function XIN clock oscillation stop detection function Voltage detection circuit On-chip Power-on reset circuit On-chip Electrical Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) Characteristics VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz) Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 2.0 A (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz) Typ. 0.7 A (VCC = 3.0 V, stop mode) Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V Programming and erasure endurance 100 times Operating Ambient Temperature -20 to 85C (N version) -40 to 85C (D version)(2) -20 to 105C (Y version)(3) Package 52-pin molded-plastic LQFP 64-pin molded-plastic FLGA
NOTES: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Specify the D version if D version functions are to be used. 3. Please contact Renesas Technology sales offices for the Y version. Rev.3.00 Feb 29, 2008 REJ03B0117-0300 Page 2 of 51
R8C/24 Group, R8C/25 Group
1. Overview
Table 1.2 CPU
Functions and Specifications for R8C/25 Group
Item Specification Number of fundamental 89 instructions instructions Minimum instruction execution 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) time 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) Operating mode Single-chip Address space 1 Mbyte Memory capacity Refer to Table 1.4 Product Information for R8C/25 Group Peripheral Ports I/O ports: 41 pins, Input port: 3 pins Functions LED drive ports I/O ports: 8 pins Timers Timer RA: 8 bits x 1 channel Timer RB: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer RD: 16 bits x 2 channels (Input capture and output compare circuits) Timer RE: With real-time clock and compare match function Serial interface 2 channels (UART0, UART1) Clock synchronous serial I/O, UART Clock synchronous serial 1 channel interface I2C bus Interface(1) Clock synchronous serial I/O with chip select LIN module Hardware LIN: 1 channel (timer RA, UART0) A/D converter 10-bit A/D converter: 1 circuit, 12 channels Watchdog timer 15 bits x 1 channel (with prescaler) Reset start selectable Interrupts Internal: 11 sources, External: 5 sources, Software: 4 sources, Priority levels: 7 levels Clock Clock generation 3 circuits circuits * XIN clock generation circuit (with on-chip feedback resistor) * On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has a frequency adjustment function * XCIN clock generation circuit (32 kHz) Real-time clock (timer RE) Oscillation stop detection function XIN clock oscillation stop detection function Voltage detection circuit On-chip Power-on reset circuit On-chip Electrical Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) Characteristics VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz) Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 2.0 A (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz) Typ. 0.7 A (VCC = 3.0 V, stop mode) Flash memory Programming and erasure voltage VCC = 2.7 to 5.5 V Programming and erasure 1,0000 times (data flash) endurance 1,000 times (program ROM) Operating Ambient Temperature -20 to 85C (N version) -40 to 85C (D version)(2) -20 to 105C (Y version)(3) Package 52-pin molded-plastic LQFP 64-pin molded-plastic FLGA NOTES: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Specify the D version if D version functions are to be used. 3. Please contact Renesas Technology sales offices for the Y version. Rev.3.00 Feb 29, 2008 REJ03B0117-0300 Page 3 of 51
R8C/24 Group, R8C/25 Group
1. Overview
1.3
Block Diagram
Figure 1.1 shows a Block Diagram.
8
8
8
6
3
3
8
I/O ports Peripheral functions
Port P0
Port P1
Port P2
Port P3
Port P4
Port P6
Timers Timer RA (8 bits) Timer RB (8 bits) Timer RD (16 bits x 2 channels) Timer RE (8 bits)
A/D converter (10 bits x 12 channels)
System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator XCIN-XCOUT
UART or clock synchronous serial I/O (8 bits x 2 channels)
I2C bus interface or clock synchronous serial I/O with chip select (8 bits x 1 channel)
LIN module (1 channel)
Watchdog timer (15 bits)
R8C/Tiny Series CPU core
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG
Memory
ROM(1)
RAM(2)
Multiplier
NOTES: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type.
Figure 1.1
Block Diagram
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 4 of 51
R8C/24 Group, R8C/25 Group
1. Overview
1.4
Product Information
Table 1.3 lists the Product Information for R8C/24 Group and Table 1.4 lists the Product Information for R8C/25 Group. Table 1.3 Product Information for R8C/24 Group ROM Capacity 16 Kbytes 24 Kbytes 32 Kbytes 48 Kbytes 64 Kbytes 16 Kbytes 32 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 48 Kbytes 64 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 48 Kbytes 64 Kbytes 16 Kbytes 32 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 48 Kbytes 64 Kbytes RAM Capacity 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes 1 Kbyte 2 Kbytes 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes 1 Kbyte 2 Kbytes 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes Package Type PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PTLG0064JA-A PTLG0064JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PTLG0064JA-A PTLG0064JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A Current of Feb. 2008 Remarks N version Blank product
Type No. R5F21244SNFP R5F21245SNFP R5F21246SNFP R5F21247SNFP R5F21248SNFP R5F21244SNLG R5F21246SNLG R5F21244SDFP R5F21245SDFP R5F21246SDFP R5F21247SDFP R5F21248SDFP R5F21244SNXXXFP R5F21245SNXXXFP R5F21246SNXXXFP R5F21247SNXXXFP R5F21248SNXXXFP R5F21244SNXXXLG R5F21246SNXXXLG R5F21244SDXXXFP R5F21245SDXXXFP R5F21246SDXXXFP R5F21247SDXXXFP R5F21248SDXXXFP
D version Blank product
N version Factory programming product(1)
D version Factory programming product(1)
NOTE: 1. The user ROM is programmed before shipment.
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 5 of 51
R8C/24 Group, R8C/25 Group
1. Overview
Type No.
R 5 F 21 24 6 S N XXX FP
Package type: FP: PLQP0052JA-A (0.65 mm pin-pitch, 10 mm square body) LG: PTLG0064JA-A (0.65 mm pin-pitch, 6 mm square body)
ROM number
Classification N: Operating ambient temperature -20C to 85C D: Operating ambient temperature -40C to 85C Y: Operating ambient temperature -20C to 105C(1) S: Low-voltage version ROM capacity 4: 16 KB 5: 24 KB 6: 32 KB 7: 48 KB 8: 64 KB R8C/24 Group R8C/Tiny Series Memory type F: Flash memory Renesas MCU Renesas semiconductor NOTE: 1. Please contact Renesas Technology sales offices for the Y version.
Figure 1.2
Type Number, Memory Size, and Package of R8C/24 Group
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 6 of 51
R8C/24 Group, R8C/25 Group
1. Overview
Table 1.4
Product Information for R8C/25 Group ROM Capacity Program ROM Data flash 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 48 Kbytes 1 Kbyte x 2 64 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 48 Kbytes 1 Kbyte x 2 64 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 48 Kbytes 1 Kbyte x 2 64 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 48 Kbytes 1 Kbyte x 2 64 Kbytes 1 Kbyte x 2 RAM Capacity 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes 1 Kbyte 2 Kbytes 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes 1 Kbyte 2 Kbytes 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes
Current of Feb. 2008 Package Type PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PTLG0064JA-A PTLG0064JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PTLG0064JA-A PTLG0064JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A Remarks N version Blank product
Type No. R5F21254SNFP R5F21255SNFP R5F21256SNFP R5F21257SNFP R5F21258SNFP R5F21254SNLG R5F21256SNLG R5F21254SDFP R5F21255SDFP R5F21256SDFP R5F21257SDFP R5F21258SDFP R5F21254SNXXXFP R5F21255SNXXXFP R5F21256SNXXXFP R5F21257SNXXXFP R5F21258SNXXXFP R5F21254SNXXXLG R5F21256SNXXXLG R5F21254SDXXXFP R5F21255SDXXXFP R5F21256SDXXXFP R5F21257SDXXXFP R5F21258SDXXXFP
D version Blank product
N version Factory programming product(1)
D version Factory programming product(1)
NOTE: 1. The user ROM is programmed before shipment.
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 7 of 51
R8C/24 Group, R8C/25 Group
1. Overview
Type No.
R 5 F 21 25 6 S N XXX FP
Package type: FP: PLQP0052JA-A (0.65 mm pin-pitch, 10 mm square body) LG: PTLG0064JA-A (0.65 mm pin-pitch, 6 mm square body)
ROM number
Classification N: Operating ambient temperature -20C to 85C D: Operating ambient temperature -40C to 85C Y: Operating ambient temperature -20C to 105C(1) S: Low-voltage version ROM capacity 4: 16 KB 5: 24 KB 6: 32 KB 7: 48 KB 8: 64 KB R8C/25 Group R8C/Tiny Series Memory type F: Flash memory Renesas MCU Renesas semiconductor NOTE: 1. Please contact Renesas Technology sales offices for the Y version.
Figure 1.3
Type Number, Memory Size, and Package of R8C/25 Group
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 8 of 51
R8C/24 Group, R8C/25 Group
1. Overview
1.5
Pin Assignments
Figure 1.4 shows PLQP0052JA-A Package Pin Assignments (Top View). Figure 1.5 shows PTLG0064JA-A Package Pin Assignments.
P6_7/INT3/RXD1
P1_2/KI2/AN10
Pin assignments (top view)
P1_0/KI0/AN8 P1_1/KI1/AN9 P3_0/TRAO P3_1/TRBO P6_5/CLK1 P0_7/AN0
P6_6/INT2/TXD1 28
39
38
37
36
35
34
33
32
31
30
29
NC P0_6/AN1 P0_5/AN2 P0_4/AN3 P4_2/VREF P6_0/TREO P6_2 P6_1 P0_3/AN4 P0_2/AN5 P0_1/AN6 P0_0/AN7 P3_7/SSO
40 41 42 43 44 45 46 47 48 49 50 51 52
10 11 12 13 1 2 3 4 5 6 7 8 9
27
P4_5/INT0
P6_3
P6_4
NC
26 25 24 23 22
NC P1_3/KI3/AN11 P1_4/TXD0 P1_5/RXD0/(TRAIO)/(INT1)(2) P1_6/CLK0 P1_7/TRAIO/INT1 P2_0/TRDIOA0/TRDCLK P2_1/TRDIOB0 P2_2/TRDIOC0 P2_3/TRDIOD0 P2_4/TRDIOA1 P2_5/TRDIOB1 P2_6/TRDIOC1
R8C/24 Group R8C/25 Group
21 20 19 18 17 16 15 14
P3_3/SSI
P3_5/SCL/SSCK
P3_4/SDA/SCS
NOTES: 1. P4_7 is an input-only port. 2. Can be assigned to the pin in parentheses by a program. NC: Non-Connection
Package: PLQP0052JA-A(52P6A-A) 0.65 mm pin pitch, 10 mm square body
Figure 1.4
PLQP0052JA-A Package Pin Assignments (Top View)
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 9 of 51
P2_7/TRDIOD1
XOUT/P4_7
MODE
P4_4/XCOUT
VSS/AVSS
RESET
P4_6/XIN
(1)
VCC/AVCC
NC
P4_3/XCIN
R8C/24 Group, R8C/25 Group
1. Overview
Pin assignments (top perspective view) A B C D E F G H
8
3
P3_3/SSI
50
P0_1/AN6
48
P0_3/AN4
46
P6_2
45
P6_0/TREO
NC
36
P6_4
NC
8
7
4
P3_4/SDA/ SCS
51
P0_0/AN7
49
P0_2/AN5
NC
44 43
P0_4/AN3
34 42
P0_5/AN2
35
NC
NC
P4_2/VREF P3_0/TRAO P6_5/CLK1
7
6
NC
5
MODE
52
P3_7/SSO
47
P6_1
33
P3_1/TRBO
6
5
7
P4_4/XCOUT
NC
6
P4_3/XCIN
2
P3_5/SCL/ SSCK
37
P6_3
NC
41
P0_6/AN1
38
P0_7/AN0
5
4
13
P2_7/ TRDIOD1
12
VCC/AVCC
NC
9
XOUT/ P4_7(1)
8
RESET
32
P1_0/KI0/ AN8
31
P1_1/KI1/ AN9
NC
4
3
NC
10
VSS/AVSS
16
P2_4/ TRDIOA1
19 20 21
23
NC
NC
NC
30
P1_2/KI2/ AN10
P1_5/RXD0/ P2_1/ TRDIOB0 (TRAIO)/(INT1)(2)
3
2
NC
11
XIN/P4_6
17 18
24
P1_4/TXD0
28
P6_6/INT2/ TXD1
NC
P2_3/ P2_0/TRDIOA0/ TRDIOD0 TRDCLK
2
1
14
P2_6/ TRDIOC1
15
P2_5/ TRDIOB1
22
25
P1_3/KI3/ AN11
27
P4_5/INT0
29
P6_7/INT3/ RXD1
P2_2/ P1_7/TRAIO/ P1_6/CLK0 TRDIOC0 INT1
1
A
B
C
D
E
F
G
H
Package: PTLG0064JA-A(64F0G) 0.65 mm pin pitch, 6 mm square body NOTES: 1. P4_7 is an input-only port. 2. Can be assigned to the pin in parentheses by a program. 3. In the figure, the numbers in circles are the pin numbers of the 52-pin LQFP package (PLQP0052JA-A). NC: Non-Connection R5F21244S NLG JAPAN
Pin assignments (top view)
Figure 1.5
PTLG0064JA-A Package Pin Assignments Page 10 of 51
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
R8C/24 Group, R8C/25 Group
1. Overview
1.6
Pin Functions
Table 1.5 lists Pin Functions. Table 1.5
Type Power supply input Analog power supply input Reset input MODE XIN clock input XIN clock output XCIN clock input XCIN clock output INT interrupt input Key input interrupt Timer RA Timer RB Timer RD
Pin Functions
Symbol VCC, VSS AVCC, AVSS RESET MODE XIN XOUT XCIN XCOUT INT0 to INT3 KI0 to KI3 TRAIO TRAO TRBO TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 TRDCLK TREO CLK0, CLK1 RXD0, RXD1 TXD0, TXD1 I/O Type I I I I I O I O I I I/O O O I/O Description Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Input "L" on this pin resets the MCU. Connect this pin to VCC via a resistor. These pins are provided for XIN clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an external clock, input it to the XIN pin and leave the XOUT pin open. These pins are provided for XCIN clock generation circuit I/O. Connect a crystal oscillator between the XCIN and XCOUT pins. To use an external clock, input it to the XCIN pin and leave the XCOUT pin open. INT interrupt input pins. INT0 is timer RD input pin. INT1 is timer RA input pin. Key input interrupt input pins Timer RA I/O pin Timer RA output pin Timer RB output pin Timer RD I/O ports
I O I/O I O I/O I/O I/O I/O I/O I/O I I I/O
External clock input pin Divided clock output pin Transfer clock I/O pin Serial data input pins Serial data output pins Clock I/O pin Data I/O pin Data I/O pin Chip-select signal I/O pin Clock I/O pin Data I/O pin Reference voltage input pin to A/D converter Analog input pins to A/D converter CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. P2_0 to P2_7 also function as LED drive ports. Input-only ports
Timer RE Serial interface
I2C
bus interface
SCL SDA SSI SCS SSCK SSO VREF AN0 to AN11 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5, P6_0 to P6_7 P4_2, P4_6, P4_7
Clock synchronous serial I/O with chip select
Reference voltage input A/D converter I/O port
Input port I: Input
I
O: Output
I/O: Input and output
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
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R8C/24 Group, R8C/25 Group
1. Overview
Table 1.6
Pin Name Information by Pin Number
I/O Pin Functions for of Peripheral Modules Clock Serial Synchronous I2C bus Timer Interface Serial I/O with Interface Chip Select SSCK SCL SSI SCS SDA
Pin Control Pin Number 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 34 35 36 37 38 41 42 43 44 45 46 47 48 49 50 51 52
Port
Interrupt
A/D Converter
P3_5 P3_3 P3_4 MODE XCIN XCOUT RESET XOUT VSS/AVSS XIN VCC/AVCC P4_3 P4_4 P4_7 P4_6 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P4_5 P6_6 P6_7 P1_2 P1_1 P1_0 P3_1 P3_0 P6_5 P6_4 P6_3 P0_7 P0_6 P0_5 P0_4 P4_2 P6_0 P6_2 P6_1 P0_3 P0_2 P0_1 P0_0 P3_7
INT1 (INT1)(1) KI3 INT0 INT2 INT3 KI2 KI1 KI0
TRDIOD1 TRDIOC1 TRDIOB1 TRDIOA1 TRDIOD0 TRDIOC0 TRDIOB0 TRDIOA0/TRDCLK TRAIO (TRAIO)(1) CLK0 RXD0 TXD0 AN11 INT0 TXD1 RXD1 AN10 AN9 AN8 TRBO TRAO CLK1
AN0 AN1 AN2 AN3 TREO
VREF
AN4 AN5 AN6 AN7 SSO
NOTE: 1. Can be assigned to the pin in parentheses by a program.
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
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R8C/24 Group, R8C/25 Group
2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank.
b31
b15
b8b7
b0
R2 R3
R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers(1)
R2 R3 A0 A1 FB
b19 b15 b0
Address registers(1) Frame base register(1)
INTBH
INTBL
Interrupt table register
The 4 high order bits of INTB are INTBH and the 16 low order bits of INTB are INTBL.
b19 b0
PC
Program counter
b15
b0
USP ISP SB
b15 b0
User stack pointer Interrupt stack pointer Static base register
FLG
b15 b8 b7 b0
Flag register
IPL
U I OBSZDC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit
NOTE: 1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 13 of 51
R8C/24 Group, R8C/25 Group
2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
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R8C/24 Group, R8C/25 Group
2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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R8C/24 Group, R8C/25 Group
3. Memory
3.
3.1
Memory
R8C/24 Group
Figure 3.1 is a Memory Map of R8C/24 Group. The R8C/24 group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2-Kbyte internal RAM area is allocated addresses 00400h to 00BFFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special Function Registers (SFRs))
002FFh
00400h
Internal RAM
0XXXh 0FFDCh
Undefined instruction Overflow BRK instruction Address match Single step
Watchdog timer/oscillation stop detection/voltage monitor
0YYYYh
Internal ROM (program ROM)
0FFFFh 1ZZZZh FFFFFh
Internal ROM (program ROM)
0FFFFh
(Reserved) (Reserved) Reset
NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Internal ROM Part Number R5F21244SNFP, R5F21244SNXXXFP, R5F21244SDFP, R5F21244SDXXXFP, R5F21244SNLG, R5F21244SNXXXLG R5F21245SNFP, R5F21245SNXXXFP, R5F21245SDFP, R5F21245SDXXXFP R5F21246SNFP, R5F21246SNXXXFP, R5F21246SDFP, R5F21246SDXXXFP, R5F21246SNLG, R5F21246SNXXXLG R5F21247SNFP, R5F21247SNXXXFP, R5F21247SDFP, R5F21247SDXXXFP R5F21248SNFP, R5F21248SNXXXFP, R5F21248SDFP, R5F21248SDXXXFP Size 16 Kbytes Address 0YYYYh 0C000h Address 1ZZZZh - - - - 13FFFh Size 1 Kbyte Internal RAM Address 0XXXXh 007FFh
24 Kbytes 32 Kbytes
0A000h 08000h
2 Kbytes 2 Kbytes
00BFFh 00BFFh
48 Kbytes 64 Kbytes
04000h 04000h
2.5 Kbytes 3 Kbytes
00DFFh 00FFFh
Figure 3.1
Memory Map of R8C/24 Group Page 16 of 51
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R8C/24 Group, R8C/25 Group
3. Memory
3.2
R8C/25 Group
Figure 3.2 is a Memory Map of R8C/25 Group. The R8C/25 group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal ROM (data flash) is allocated addresses 02400h to 02BFFh. The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 2-Kbyte internal RAM is allocated addresses 00400h to 00BFFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special Function Registers (SFRs))
002FFh
00400h
Internal RAM
0XXXXh 02400h
Internal ROM (data flash)(1)
02BFFh
0FFDCh
Undefined instruction Overflow BRK instruction Address match Single step
Watchdog timer/oscillation stop detection/voltage monitor
0YYYYh
Internal ROM (program ROM)
0FFFFh 1ZZZZh FFFFFh
Internal ROM (program ROM)
0FFFFh
(Reserved) (Reserved) Reset
NOTES: 1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown. 2. The blank regions are reserved. Do not access locations in these regions. Internal ROM Part Number R5F21254SNFP, R5F21254SNXXXFP, R5F21254SDFP, R5F21254SDXXXFP, R5F21254SNLG, R5F21254SNXXXLG R5F21255SNFP, R5F21255SNXXXFP, R5F21255SDFP, R5F21255SDXXXFP R5F21256SNFP, R5F21256SNXXXFP, R5F21256SDFP, R5F21256SDXXXFP, R5F21256SNLG, R5F21256SNXXXLG R5F21257SNFP, R5F21257SNXXXFP, R5F21257SDFP, R5F21257SDXXXFP R5F21258SNFP, R5F21258SNXXXFP, R5F21258SDFP, R5F21258SDXXXFP Size 16 Kbytes Address 0YYYYh 0C000h Address 1ZZZZh - - - - 13FFFh Size 1 Kbyte Internal RAM Address 0XXXXh 007FFh
24 Kbytes 32 Kbytes
0A000h 08000h
2 Kbytes 2 Kbytes
00BFFh 00BFFh
48 Kbytes 64 Kbytes
04000h 04000h
2.5 Kbytes 3 Kbytes
00DFFh 00FFFh
Figure 3.2
Memory Map of R8C/25 Group
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R8C/24 Group, R8C/25 Group
4. Special Function Registers (SFRs)
4.
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special function registers. Table 4.1
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Eh 003Fh X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect this register. 3. The LVD0ON bit in the OFS register is set to 1 and hardware reset. 4. Power-on reset, voltage monitor 0 reset or the LVD0ON bit in the OFS register is set to 0, and hardware reset. 5. Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect b2 and b3. 6. The CSPROINI bit in the OFS register is set to 0.
SFR Information (1)(1)
Register Symbol After reset
Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1
PM0 PM1 CM0 CM1
00h 00h 01101000b 00100000b
Protect Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0
PRCR OCD WDTR WDTS WDC RMAD0
00h 00000100b XXh XXh 00X11111b 00h 00h 00h 00h 00h 00h 00h
Address Match Interrupt Enable Register Address Match Interrupt Register 1
AIER RMAD1
Count Source Protection Mode Register
CSPR
00h 10000000b(6)
High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2
FRA0 FRA1 FRA2
00h When shipping 00h
Clock Prescaler Reset Flag High-Speed On-Chip Oscillator Control Register 4 High-Speed On-Chip Oscillator Control Register 6 High-Speed On-Chip Oscillator Control Register 7
CPSRF FRA4 FRA6 FRA7
00h When shipping When shipping When shipping
Voltage Detection Register 1(2) Voltage Detection Register 2(2)
VCA1 VCA2
00001000b 00h(3) 00100000b(4)
Voltage Monitor 1 Circuit Control Register(5) Voltage Monitor 2 Circuit Control Register(5) Voltage Monitor 0 Circuit Control Register(2)
VW1C VW2C VW0C
00001000b 00h 0000X000b(3) 0100X001b(4)
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R8C/24 Group, R8C/25 Group
4. Special Function Registers (SFRs)
Table 4.2
Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh
SFR Information (2)(1)
Register Symbol After reset
Timer RD0 Interrupt Control Register Timer RD1 Interrupt Control Register Timer RE Interrupt Control Register
TRD0IC TRD1IC TREIC
XXXXX000b XXXXX000b XXXXX000b
Key Input Interrupt Control Register A/D Conversion Interrupt Control Register SSU/IIC Interrupt Control Register(2) UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register INT2 Interrupt Control Register Timer RA Interrupt Control Register Timer RB Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register
KUPIC ADIC SSUIC / IICIC S0TIC S0RIC S1TIC S1RIC INT2IC TRAIC TRBIC INT1IC INT3IC
XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XXXXX000b XXXXX000b XX00X000b XX00X000b
INT0 Interrupt Control Register
INT0IC
XX00X000b
X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Selected by the IICSEL bit in the PMR register.
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R8C/24 Group, R8C/25 Group
4. Special Function Registers (SFRs)
Table 4.3
Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh
SFR Information (3)(1)
Register Symbol After reset
UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register
U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB
00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh
SS Control Register H / IIC bus Control Register 1(2) SS Control Register L / IIC bus Control Register 2(2) SS Mode Register / IIC bus Mode Register(2) SS Enable Register / IIC bus Interrupt Enable Register(2) SS Status Register / IIC bus Status Register(2) SS Mode Register 2 / Slave Address Register(2) SS Transmit Data Register / IIC bus Transmit Data Register(2) SS Receive Data Register / IIC bus Receive Data Register(2)
SSCRH / ICCR1 SSCRL / ICCR2 SSMR / ICMR SSER / ICIER SSSR / ICSR SSMR2 / SAR SSTDR / ICDRT SSRDR / ICDRR
00h 01111101b 00011000b 00h 00h / 0000X000b 00h FFh FFh
X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Selected by the IICSEL bit in the PMR register.
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R8C/24 Group, R8C/25 Group
4. Special Function Registers (SFRs)
Table 4.4
Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh
SFR Information (4)(1)
Register A/D Register AD Symbol XXh XXh After reset
A/D Control Register 2 A/D Control Register 0 A/D Control Register 1
ADCON2 ADCON0 ADCON1
00h 00h 00h
Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P4 Direction Register Port P6 Register Port P6 Direction Register
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 PD4 P6 PD6
XXh XXh 00h 00h XXh XXh 00h 00h XXh 00h XXh 00h
Port P2 Drive Capacity Control Register UART1 Function Select Register
P2DRR U1SR
00h XXh
Port Mode Register External Input Enable Register INT Input Filter Select Register Key Input Enable Register Pull-Up Control Register 0 Pull-Up Control Register 1
PMR INTEN INTF KIEN PUR0 PUR1
00h 00h 00h 00h 00h XX00XX00b
X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions.
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R8C/24 Group, R8C/25 Group
4. Special Function Registers (SFRs)
Table 4.5
Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh
SFR Information (5)(1)
Register Timer RA Control Register Timer RA I/O Control Register Timer RA Mode Register Timer RA Prescaler Register Timer RA Register LIN Control Register LIN Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register Symbol TRACR TRAIOC TRAMR TRAPRE TRA LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR After reset 00h 00h 00h FFh FFh 00h 00h 00h 00h 00h 00h FFh FFh FFh
Timer RE Second Data Register / Counter Data Register Timer RE Minute Data Register / Compare Data Register Timer RE Hour Data Register Timer RE Day of Week Data Register Timer RE Control Register 1 Timer RE Control Register 2 Timer RE Count Source Select Register
TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 TRECSR
00h 00h 00h 00h 00h 00h 00001000b
Timer RD Start Register Timer RD Mode Register Timer RD PWM Mode Register Timer RD Function Control Register Timer RD Output Master Enable Register 1 Timer RD Output Master Enable Register 2 Timer RD Output Control Register Timer RD Digital Filter Function Select Register 0 Timer RD Digital Filter Function Select Register 1
TRDSTR TRDMR TRDPMR TRDFCR TRDOER1 TRDOER2 TRDOCR TRDDF0 TRDDF1
11111100b 00001110b 10001000b 10000000b FFh 01111111b 00h 00h 00h
X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions.
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R8C/24 Group, R8C/25 Group
4. Special Function Registers (SFRs)
Table 4.6
Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh
SFR Information (6)(1)
Register Timer RD Control Register 0 Timer RD I/O Control Register A0 Timer RD I/O Control Register C0 Timer RD Status Register 0 Timer RD Interrupt Enable Register 0 Timer RD PWM Mode Output Level Control Register 0 Timer RD Counter 0 Timer RD General Register A0 Timer RD General Register B0 Timer RD General Register C0 Timer RD General Register D0 Timer RD Control Register 1 Timer RD I/O Control Register A1 Timer RD I/O Control Register C1 Timer RD Status Register 1 Timer RD Interrupt Enable Register 1 Timer RD PWM Mode Output Level Control Register 1 Timer RD Counter 1 Timer RD General Register A1 Timer RD General Register B1 Timer RD General Register C1 Timer RD General Register D1 Symbol TRDCR0 TRDIORA0 TRDIORC0 TRDSR0 TRDIER0 TRDPOCR0 TRD0 TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDCR1 TRDIORA1 TRDIORC1 TRDSR1 TRDIER1 TRDPOCR1 TRD1 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1 After reset 00h 10001000b 10001000b 11100000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00h 10001000b 10001000b 11000000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh
X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions.
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R8C/24 Group, R8C/25 Group
4. Special Function Registers (SFRs)
Table 4.7
Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh FFFFh
SFR Information (7)(1)
Register Symbol After reset
Flash Memory Control Register 4 Flash Memory Control Register 1 Flash Memory Control Register 0
FMR4 FMR1 FMR0
01000000b 1000000Xb 00000001b
Option Function Select Register
OFS
(Note 2)
X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
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R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
5.
Electrical Characteristics
The electrical characteristics of N version (Topr = -20 to 85C) and D version (Topr = -40 to 85C) are listed below. Please contact Renesas Technology sales offices for the electrical characteristics in the Y version (Topr = -20 to 105C). Table 5.1
Symbol VCC/AVCC VI VO Pd Topr Tstg Supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature Topr = 25C
Absolute Maximum Ratings
Parameter Condition Rated Value -0.3 to 6.5 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 500(1) -20 to 85 (N version) / -40 to 85 (D version) -65 to 150 Unit V V V mW C C
NOTE: 1. 300 mW for the PTLG0064JA-A package.
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R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Table 5.2
Symbol VCC/AVCC VSS/AVSS VIH VIL IOH(sum) IOH(sum) IOH(peak) IOH(avg) IOL(sum) IOL(sum) IOL(peak) IOL(avg) f(XIN)
Recommended Operating Conditions
Parameter Supply voltage Supply voltage Input "H" voltage Input "L" voltage Peak sum output "H" current Average sum output "H" current Peak output "H" current Average output "H" current Peak sum output "L" current Average sum output "L" current Peak output "L" current Average output "L" current Sum of all pins IOH(peak) Sum of all pins IOH(avg) Except P2_0 to P2_7 P2_0 to P2_7 Except P2_0 to P2_7 P2_0 to P2_7 Sum of all pins IOL(peak) Sum of all pins IOL(avg) Except P2_0 to P2_7 P2_0 to P2_7 Except P2_0 to P2_7 P2_0 to P2_7 3.0 V VCC 5.5 V 2.7 V VCC < 3.0 V 2.2 V VCC < 2.7 V Conditions Standard Min. 2.2 - 0.8 VCC 0 - - - - - - - - - - - - 0 0 0 0 0 0 0 - Typ. - 0 - - - - - - - - - - - - - - - - - - - - - 125 Max. 5.5 - VCC 0.2 VCC -160 -80 -10 -40 -5 -20 160 80 10 40 5 20 20 10 5 70 20 10 5 - Unit V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz MHz kHz MHz MHz MHz kHz
XIN clock input oscillation frequency
f(XCIN) -
XCIN clock input oscillation frequency System clock OCD2 = 0 XlN clock selected OCD2 = 1 On-chip oscillator clock selected
2.2 V VCC 5.5 V 3.0 V VCC 5.5 V 2.7 V VCC < 3.0 V 2.2 V VCC < 2.7 V FRA01 = 0 Low-speed on-chip oscillator clock selected FRA01 = 1 High-speed on-chip oscillator clock selected 3.0 V VCC 5.5 V FRA01 = 1 High-speed on-chip oscillator clock selected 2.7 V VCC 5.5 V FRA01 = 1 High-speed on-chip oscillator clock selected 2.2 V VCC 5.5 V
-
-
20
MHz
-
-
10
MHz
-
-
5
MHz
NOTES: 1. VCC = 2.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. The average output current indicates the average value of current measured during 100 ms.
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R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Table 5.3
Symbol - -
A/D Converter Characteristics
Parameter Resolution Absolute accuracy 10-bit mode 8-bit mode 10-bit mode 8-bit mode 10-bit mode 8-bit mode Vref = AVCC AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 3.3 V AD = 10 MHz, Vref = AVCC = 3.3 V AD = 5 MHz, Vref = AVCC = 2.2 V AD = 5 MHz, Vref = AVCC = 2.2 V Vref = AVCC AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 5.0 V 8-bit mode Conditions Standard Min. - - - - - - - 10 3.3 2.8 2.2 0 Vref = AVCC = 2.7 to 5.5 V Vref = AVCC = 2.7 to 5.5 V Vref = AVCC = 2.2 to 5.5 V Vref = AVCC = 2.2 to 5.5 V 0.25 1 0.25 1 Without sample and hold With sample and hold Without sample and hold With sample and hold Typ. - - - - - - - - - - - - - - - - Max. 10 3 2 5 2 5 2 40 - - AVCC AVCC 10 10 5 5 Unit Bit LSB LSB LSB LSB LSB LSB k s s V V MHz MHz MHz MHz
Rladder tconv Vref VIA -
Resistor ladder Conversion time 10-bit mode Reference voltage Analog input voltage(2) A/D operating clock frequency
NOTES: 1. AVCC = 2.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode.
P0 P1 P2 P3 P4 P6
30pF
Figure 5.1
Ports P0 to P4, P6 Timing Measurement Circuit
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R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Table 5.4
Symbol - - - td(SR-SUS) - - - - - - -
Flash Memory (Program ROM) Electrical Characteristics
Parameter Program/erase endurance(2) Byte program time Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time(7) Ambient temperature = 55C Conditions R8C/24 Group R8C/25 Group Standard Min. 100(3) 1,000(3) - - - 650 0 - 2.7 2.2 0 20 Typ. - - 50 0.4 - - - - - - - - Max. - - 400 9 97+CPU clock x 6 cycles - - 3+CPU clock x 4 cycles 5.5 5.5 60 - Unit times times s s s s ns s V V C year
NOTES: 1. VCC = 2.7 to 5.5 V at Topr = 0 to 60C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied.
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R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Table 5.5
Symbol - - - - - td(SR-SUS) - - - - - - -
Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Parameter Program/erase endurance(2) Byte program time (program/erase endurance 1,000 times) Byte program time (program/erase endurance > 1,000 times) Block erase time (program/erase endurance 1,000 times) Block erase time (program/erase endurance > 1,000 times) Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time(9) Ambient temperature = 55 C Conditions Standard Min. 10,000(3) - - - - - 650 0 - 2.7 2.2 -20(8) 20 Typ. - 50 65 0.2 0.3 - - - - - - - - Max. - 400 - 9 - 97+CPU clock x 6 cycles - - 3+CPU clock x 4 cycles 5.5 5.5 85 - Unit times s s s s s s ns s V V C year
NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times is the same as that in program ROM. 5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 8. -40C for D version. 9. The data hold time includes time that the power supply is off or the clock is not supplied.
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R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Suspend request (maskable interrupt request)
FMR46
Fixed time Clock-dependent time Access restart
td(SR-SUS)
Figure 5.2
Time delay until Suspend
Table 5.6
Symbol Vdet0 - td(E-A) Vccmin
Voltage Detection 0 Circuit Electrical Characteristics
Parameter Voltage detection level Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(2) MCU operating voltage minimum value VCA25 = 1, VCC = 5.0 V Condition Standard Min. 2.2 - - 2.2 Typ. 2.3 0.9 - - Max. 2.4 - 300 - Unit V A s V
NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0.
Table 5.7
Symbol Vdet1 - - td(E-A)
Voltage Detection 1 Circuit Electrical Characteristics
Parameter Voltage detection level Voltage monitor 1 interrupt request generation time(2) VCA26 = 1, VCC = 5.0 V Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) Condition Standard Min. 2.70 - - - Typ. 2.85 40 0.6 - Max. 3.00 - - 100 Unit V s A s
NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0.
Table 5.8
Symbol Vdet2 - - td(E-A)
Voltage Detection 2 Circuit Electrical Characteristics
Parameter Voltage detection level Voltage monitor 2 interrupt request generation time(2) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) VCA27 = 1, VCC = 5.0 V Condition Standard Min. 3.3 - - - Typ. 3.6 40 0.6 - Max. 3.9 - - 100 Unit V s A s
NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0.
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5. Electrical Characteristics
Table 5.9
Symbol Vpor1 Vpor2 trth
Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Parameter Power-on reset valid voltage(4) Power-on reset or voltage monitor 0 reset valid voltage External power VCC rise gradient(2) Condition Min. - 0 20 Standard Typ. - - - Max. 0.1 Vdet0 - V V mV/msec Unit
NOTES: 1. The measurement condition is Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. This condition (external power VCC rise gradient) does not apply if VCC 1.0 V. 3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1. 4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20C Topr 85C, maintain tw(por1) for 3,000 s or more if -40C Topr < -20C.
Vdet0(3)
2.2 V
External Power VCC
trth
trth
Vdet0(3)
Vpor2
Vpor1 tw(por1) Sampling time(1, 2)
Internal reset signal ("L" valid) 1 x 32 fOCO-S
1 x 32 fOCO-S
NOTES: 1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage range (2.2 V or above) during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details. 3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.
Figure 5.3
Power-on Reset Circuit Electrical Characteristics
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5. Electrical Characteristics
Table 5.10
Symbol fOCO40M
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Parameter High-speed on-chip oscillator frequency temperature * supply voltage dependence Condition VCC = 4.75 to 5.25 V 0C Topr 60C(2) VCC = 4.5 to 5.5 V -20C Topr 85C VCC = 4.5 to 5.5 V -40C Topr 85C VCC = 3.0 to 5.5 V -20C Topr 85C(2) VCC = 3.0 to 5.5 V -40C Topr 85C(2) VCC = 2.7 to 5.5 V -20C Topr 85C(2) VCC = 2.7 to 5.5 V -40C Topr 85C(2) VCC = 2.2 to 5.5 V -20C Topr 85C(3) VCC = 2.2 to 5.5 V -40C Topr 85C(3) High-speed on-chip oscillator frequency when correction value in FRA7 register is written to FRA1 register(4) VCC = 5.0 V, Topr = 25C VCC = 3.0 to 5.5 V -20C Topr 85C Adjust FRA1 register (value after reset) to -1 VCC = 5.0 V, Topr = 25C Standard Min. 39.2 38.8 38.4 38.8 38.4 38 37.6 35.2 34 - -3% 08h - - - Typ. 40 40 40 40 40 40 40 40 40 36.864 - - +0.3 10 400 3% F7h - 100 - Max. 40.8 40.8 40.8 41.2 41.6 42 42.4 44.8 46 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz % - MHz s A
- - - -
Value in FRA1 register after reset Oscillation frequency adjustment unit of highspeed on-chip oscillator Oscillation stability time Self power consumption at oscillation
NOTES: 1. VCC = 2.2 to 5.5 V, Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. Standard values when the FRA1 register value after reset is assumed. 3. Standard values when the corrected value of the FRA6 register has been written to the FRA1 register. 4. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in UART mode.
Table 5.11
Symbol fOCO-S - -
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Parameter Low-speed on-chip oscillator frequency Oscillation stability time Self power consumption at oscillation VCC = 5.0 V, Topr = 25C Condition Standard Min. 30 - - Typ. 125 10 15 Max. 250 100 - Unit kHz s A
NOTE: 1. VCC = 2.2 to 5.5 V, Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.
Table 5.12
Symbol td(P-R) td(R-S)
Power Supply Circuit Timing Characteristics
Parameter Time for internal power supply stabilization during power-on(2) STOP exit time(3) Condition Standard Min. 1 - Typ. - - Max. 2000 150 Unit s s
NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
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5. Electrical Characteristics
Table 5.13
Symbol tSUCYC tHI tLO tRISE tFALL tSU tH tLEAD tLAG tOD tSA tOR
Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Parameter SSCK clock cycle time SSCK clock "H" width SSCK clock "L" width SSCK clock rising time SSCK clock falling time Master Slave Master Slave Conditions Standard Min. 4 0.4 0.4 - - - - 100 1 1tCYC + 50 1tCYC + 50 - 2.7 V VCC 5.5 V 2.2 V VCC < 2.7 V SSI slave out open time 2.7 V VCC 5.5 V 2.2 V VCC < 2.7 V - - - - Typ. - - - - - - - - - - - - - - - - Max. - 0.6 0.6 1 1 1 1 - - - - 1 1.5tCYC + 100 1.5tCYC + 200 1.5tCYC + 100 1.5tCYC + 200 tCYC(2) tSUCYC tSUCYC tCYC(2) s tCYC(2) s ns tCYC(2) ns ns tCYC(2) ns ns ns ns Unit
SSO, SSI data input setup time SSO, SSI data input hold time SCS setup time SCS hold time SSI slave access time Slave Slave
SSO, SSI data output delay time
NOTES: 1. VCC = 2.2 to 5.5 V, VSS = 0 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. 1tCYC = 1/f1(s)
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5. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIH or VOH tHI tFALL tRISE
SSCK (output) (CPOS = 1)
tLO tHI
SSCK (output) (CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIH or VOH tHI tFALL tRISE
SSCK (output) (CPOS = 1)
tLO tHI
SSCK (output) (CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
CPHS, CPOS: Bits in SSMR register
Figure 5.4
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
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5. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIH or VOH tLEAD tHI tFALL tRISE tLAG
SSCK (input) (CPOS = 1)
tLO tHI
SSCK (input) (CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0 SCS (input)
VIH or VOH VIH or VOH tLEAD tHI tFALL tRISE tLAG
SSCK (input) (CPOS = 1)
tLO tHI
SSCK (input) (CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.5
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
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R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
tHI VIH or VOH
SSCK
VIH or VOH tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
Figure 5.6
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous Communication Mode)
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R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Table 5.14
Symbol tSCL tSCLH tSCLL tsf tSP tBUF tSTAH tSTAS tSTOP tSDAS tSDAH
Timing Requirements of I2C bus Interface(1)
Parameter SCL input cycle time SCL input "H" width SCL input "L" width SCL, SDA input fall time SCL, SDA input spike pulse rejection time SDA input bus-free time Start condition input hold time Retransmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time Condition Standard Typ. - 12tCYC + 600(2) - 3tCYC + 300(2) Min. 5tCYC + - - 500(2)
- - - - - - - - -
Unit Max. -
- -
ns ns ns ns ns ns ns ns ns ns ns
300 1tCYC(2) -
- - - - -
5tCYC(2) 3tCYC(2) 3tCYC(2) 3tCYC(2) 1tCYC + 20(2) 0
NOTES: 1. VCC = 2.2 to 5.5 V, VSS = 0 V and Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. 1tCYC = 1/f1(s)
VIH
SDA
VIL tBUF tSTAH tSCLH tSTAS tSP tSTOP
SCL
P(2) S(1) tsf tSCLL tSCL Sr(3) tsr tSDAH tSDAS P(2)
NOTES: 1. Start condition 2. Stop condition 3. Retransmit start condition
Figure 5.7
I/O Timing of I2C bus Interface
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R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Table 5.15
Symbol VOH
Electrical Characteristics (1) [VCC = 5 V]
Parameter Condition IOH = -5 mA IOH = -200 A Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 5 mA IOL = 200 A Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW Standard Min. Typ. VCC - 2.0 - VCC - 0.5 - VCC - 2.0 - VCC - 2.0 - VCC - 2.0 - VCC - 2.0 - - - - - - - - - - - - - 0.1 0.5 Max. VCC VCC VCC VCC VCC VCC 2.0 0.45 2.0 2.0 2.0 2.0 - Unit V V V V V V V V V V V V V
Output "H" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7 XOUT
IOH = -20 mA IOH = -5 mA IOH = -1 mA IOH = -500 A
VOL
Output "L" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7 XOUT
IOL = 20 mA IOL = 5 mA IOL = 1 mA IOL = 500 A
VT+-VT-
Hysteresis
INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, CLK1, SSI, SCL, SDA, SSO RESET VI = 5 V, Vcc = 5V VI = 0 V, Vcc = 5V VI = 0 V, Vcc = 5V XIN XCIN During stop mode
0.1
- -
1.0
- -
-
V
A A k M
IIH IIL RPULLUP RfXIN RfXCIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance Feedback resistance RAM hold voltage
30 -
-
50 1.0 18
-
5.0 -5.0 167 -
- -
M V
1.8
NOTE: 1. VCC = 4.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 20 MHz, unless otherwise specified.
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5. Electrical Characteristics
Table 5.16
Electrical Characteristics (2) [Vcc = 5 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Parameter Condition XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz Program operation on RAM Flash memory off, FMSTP = 1 Min. - Standard Typ. Max. 10 17 Unit mA
Symbol ICC
Power supply High-speed current clock mode (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS
-
9
15
mA
-
6
-
mA
-
5
-
mA
-
4
-
mA
-
2.5
-
mA
High-speed on-chip oscillator mode
-
10
15
mA
-
4
-
mA
-
5.5
10
mA
-
2.5
-
mA
Low-speed on-chip oscillator mode Low-speed clock mode
-
130
300
A
-
130
300
A
-
30
-
A
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5. Electrical Characteristics
Table 5.17
Electrical Characteristics (3) [Vcc = 5 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Parameter Condition XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 Increase during Without sample & hold A/D converter With sample & hold operation Stop mode XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. - Standard Typ. Max. 25 75 Unit
A
Symbol ICC
Power supply Wait mode current (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS
-
23
60
A
-
4.0
-
A
-
2.2
-
A
- - -
2.6 1.6 0.8
- -
mA mA
A
3.0
-
1.2
-
A
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R8C/24 Group, R8C/25 Group Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25C) [VCC = 5 V] Table 5.18
Symbol tc(XIN) tWH(XIN) tWL(XIN) tc(XCIN) tWH(XCIN) tWL(XCIN) XIN input cycle time XIN input "H" width XIN input "L" width XCIN input cycle time XCIN input "H" width XCIN input "L" width
5. Electrical Characteristics
XIN Input, XCIN Input
Parameter Standard Min. Max. 50 - 25 - 25 - 14 - 7 - 7 - Unit ns ns ns s s s
tC(XIN) tWH(XIN)
VCC = 5 V
XIN input
tWL(XIN) tC(XCIN) tWH(XCIN)
XCIN input
tWL(XCIN)
Figure 5.8
XIN Input and XCIN Input Timing Diagram when VCC = 5 V
Table 5.19
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. Max. 100 - 40 - 40 - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 5 V
TRAIO input
tWL(TRAIO)
Figure 5.9
TRAIO Input Timing Diagram when VCC = 5 V
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R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Table 5.20
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 1
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 200 - 100 - 100 - - 50 0 - 50 - 90 - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 5 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0 or 1
Figure 5.10
Serial Interface Timing Diagram when VCC = 5 V
Table 5.21
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0 to 3) Input
Parameter INT0 input "H" width INT0 input "L" width Standard Min. Max. - 250(1) 250(2)
-
Unit ns ns
NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
tW(INL)
INTi input
tW(INH)
i = 0 to 3
Figure 5.11
External Interrupt INTi Input Timing Diagram when VCC = 5 V
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5. Electrical Characteristics
Table 5.22
Symbol VOH
Electrical Characteristics (3) [VCC = 3 V]
Parameter Condition IOH = -1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOH = -5 mA IOH = -1 mA IOH = -0.1 mA IOH = -50 A Min. VCC - 0.5 VCC - 0.5 VCC - 0.5 VCC - 0.5 VCC - 0.5
-
Output "H" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7
Standard Typ. -
- - - - - - - - -
Max. VCC VCC VCC VCC VCC 0.5 0.5 0.5 0.5 0.5
-
Unit V V V V V V V V V V V
XOUT
VOL
Output "L" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7
IOL = 5 mA IOL = 1 mA IOL = 0.1 mA IOL = 50 A
- - - -
XOUT
VT+-VT-
Hysteresis
INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, CLK1, SSI, SCL, SDA, SSO RESET VI = 3 V, Vcc = 3V VI = 0 V, Vcc = 3V VI = 0 V, Vcc = 3V XIN XCIN During stop mode
0.1
0.3
0.1
- -
0.4
- -
-
V
A A k M M V
IIH IIL RPULLUP RfXIN RfXCIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance Feedback resistance RAM hold voltage
66 - - 1.8
160 3.0 18 -
4.0 -4.0 500 - - -
NOTE: 1. VCC =2.7 to 3.3 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 10 MHz, unless otherwise specified.
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 43 of 51
R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Table 5.23
Electrical Characteristics (4) [Vcc = 3 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Parameter Condition XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz Program operation on RAM Flash memory off, FMSTP = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 Without sample & hold With sample & hold XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. - Standard Typ. Max. 6 - Unit mA
Symbol ICC
Power supply current High-speed (VCC = 2.7 to 3.3 V) clock mode Single-chip mode, output pins are open, other pins are VSS
-
2
-
mA
High-speed onchip oscillator mode
-
5
9
mA
-
2
-
mA
Low-speed onchip oscillator mode Low-speed clock mode
-
130
300
A
-
130
300
A
-
30
-
A
Wait mode
-
25
70
A
-
23
55
A
-
3.8
-
A
-
2.0
-
A
Increase during A/D converter operation Stop mode
- - -
0.9 0.5 0.7
- -
mA mA
A
3.0
-
1.1
-
A
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 44 of 51
R8C/24 Group, R8C/25 Group Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25C) [VCC = 3 V] Table 5.24
Symbol tc(XIN) tWH(XIN) tWL(XIN) tc(XCIN) tWH(XCIN) tWL(XCIN) XIN input cycle time XIN input "H" width XIN input "L" width XCIN input cycle time XCIN input "H" width XCIN input "L" width
5. Electrical Characteristics
XIN Input, XCIN Input
Parameter Standard Min. Max. 100 - 40 - 40 - 14 - 7 - 7 - Unit ns ns ns s s s
tC(XIN) tWH(XIN)
VCC = 3 V
XIN input
tWL(XIN) tC(XCIN) tWH(XCIN)
XCIN input
tWL(XCIN)
Figure 5.12
XIN Input and XCIN Input Timing Diagram when VCC = 3 V
Table 5.25
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. Max. 300 - 120 - 120 - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 3 V
TRAIO input
tWL(TRAIO)
Figure 5.13
TRAIO Input Timing Diagram when VCC = 3 V
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 45 of 51
R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Table 5.26
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 1
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi Input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 300 - 150 - 150 - - 80 0 - 70 - 90 - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 3 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0 or 1
Figure 5.14
Serial Interface Timing Diagram when VCC = 3 V
Table 5.27
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0 to 3) Input
Parameter INT0 input "H" width INT0 input "L" width Standard Min. Max. - 380(1) 380(2)
-
Unit ns ns
NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
tW(INL)
INTi input
tW(INH)
i = 0 to 3
Figure 5.15
External Interrupt INTi Input Timing Diagram when VCC = 3 V
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 46 of 51
R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Table 5.28
Symbol VOH
Electrical Characteristics (5) [VCC = 2.2 V]
Parameter Condition IOH = -1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOH = -2 mA IOH = -1 mA IOH = -0.1 mA IOH = -50 A Min. VCC - 0.5 VCC - 0.5 VCC - 0.5 VCC - 0.5 VCC - 0.5
-
Output "H" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7
Standard Typ. -
- - - - - - - - -
Max. VCC VCC VCC VCC VCC 0.5 0.5 0.5 0.5 0.5
-
Unit V V V V V V V V V V V
XOUT
VOL
Output "L" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7
IOL = 2 mA IOL = 1 mA IOL = 0.1 mA IOL = 50 A
- - - -
XOUT
VT+-VT-
Hysteresis
INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, CLK1, SSI, SCL, SDA, SSO RESET VI = 2.2 V VI = 0 V VI = 0 V XIN XCIN During stop mode
0.05
0.3
0.05
- -
0.15
- -
-
V
A A k M M V
IIH IIL RPULLUP RfXIN RfXCIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance Feedback resistance RAM hold voltage
100 - - 1.8
200 5 35 -
4.0 -4.0 600 - - -
NOTE: 1. VCC = 2.2 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 5 MHz, unless otherwise specified.
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 47 of 51
R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Table 5.29
Electrical Characteristics (6) [Vcc = 2.2 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Parameter Condition XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 5 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 5 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz Program operation on RAM Flash memory off, FMSTP = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 Without sample & hold With sample & hold XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. - Standard Typ. Max. 3.5 - Unit mA
Symbol ICC
Power supply current High-speed clock (VCC = 2.2 to 2.7 V) mode Single-chip mode, output pins are open, other pins are VSS
-
1.5
-
mA
High-speed onchip oscillator mode
-
3.5
-
mA
-
1.5
-
mA
Low-speed onchip oscillator mode Low-speed clock mode
-
100
230
A
-
100
230
A
-
25
-
A
Wait mode
-
22
60
A
-
20
55
A
-
3.0
-
A
-
1.8
-
A
Increase during A/D converter operation Stop mode
- - -
0.4 0.3 0.7
- -
mA mA
A
3.0
-
1.1
-
A
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 48 of 51
R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Timing requirements (Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25C) [VCC = 2.2 V] Table 5.30
Symbol tc(XIN) tWH(XIN) tWL(XIN) tc(XCIN) tWH(XCIN) tWL(XCIN) XIN input cycle time XIN input "H" width XIN input "L" width XCIN input cycle time XCIN input "H" width XCIN input "L" width
XIN Input, XCIN Input
Parameter Standard Min. Max. 200 - 90 - 90 - 14 - 7 - 7 - Unit ns ns ns s s s
tC(XIN) tWH(XIN)
VCC = 2.2 V
XIN input
tWL(XIN) tC(XCIN) tWH(XCIN)
XCIN input
tWL(XCIN)
Figure 5.16
XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V
Table 5.31
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. Max. 500 - 200 - 200 - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 2.2 V
TRAIO input
tWL(TRAIO)
Figure 5.17
TRAIO Input Timing Diagram when VCC = 2.2 V
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 49 of 51
R8C/24 Group, R8C/25 Group
5. Electrical Characteristics
Table 5.32
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 1
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 800 - 400 - 400 - - 200 0 - 150 - 90 - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 2.2 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0 or 1
Figure 5.18
Serial Interface Timing Diagram when VCC = 2.2 V
Table 5.33
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0 to 3) Input
Parameter INT0 input "H" width INT0 input "L" width Standard Min. Max. (1) - 1000 1000(2)
-
Unit ns ns
NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
tW(INL)
INTi input
tW(INH)
i = 0 to 3
Figure 5.19
External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 50 of 51
R8C/24 Group, R8C/25 Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Technology website.
JEITA Package Code P-LQFP52-10x10-0.65 RENESAS Code PLQP0052JA-A Previous Code 52P6A-A MASS[Typ.] 0.3g
Under development
HD *1 39 D 27
40
26 bp b1
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
*2
HE
E
c1
c
Reference Symbol
Dimension in Millimeters
14
1 ZD Index mark
13
ZE
52
Terminal cross section
A2
A
c
F
e
y
*3
L bp x Detail F L1
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
Nom 10.0 10.0 1.4 11.8 12.0 11.8 12.0 0.05 0.27 0.09 0
Min 9.9 9.9
Max 10.1 10.1
0.35
12.2 12.2 1.7 0.1 0.15 0.32 0.37 0.30 0.145 0.20 0.125 8 0.65 0.13 0.10 1.1 1.1 0.5 0.65 1.0
JEITA Package Code P-TFLGA64-6x6-0.65
RENESAS Code PTLG0064JA-A
Previous Code 64F0G
MASS[Typ.] 0.07g
A1
b1
S b
AB S AB
wSB
D
wSA A
e
H G F E
E
D C B A
Reference Symbol
e
Dimension in Millimeters
x4 v Index mark (Laser mark)
yS
1
2
3
4
5
6
7
8
Index mark
D E v w A e b b1 x y
Nom Max 6.0 6.0 0.15 0.20 1.05 0.65 0.31 0.35 0.39 0.39 0.43 0.47 0.08 0.10
Min
Rev.3.00 Feb 29, 2008 REJ03B0117-0300
Page 51 of 51
REVISION HISTORY REVISION HISTORY
Rev. 0.01 0.02 Date Sep 17, 2004 Dec 10, 2004
R8C/24 Group, R8C/25 Group Datasheet R8C/24 Group, R8C/25 Group Datasheet
Description
Page 2, 3 First Edition issued
Summary
All pages Part Number revised. R8C/26 R8C/24, R8C/27 R8C/25 Table 1.1 R8C/24 Group Performance, Table 1.2 R8C/25 Group Performance - Serial Interface: I2C Bus Interface and Chip-select clock synchronous (SSU) added. - LIN Module added. - Interrupt: Internal factors revised; 10 11 - Note on Operating Ambient Temperature added. Figure 1.1 Block Diagram - LIN Module added. - Chip-select clock synchronous (SSU) is added to I2C Bus Interface. Table 1.3 Product Information of R8C/24 Group, Table 1.4 Product Information of R8C/25 Group Date and Development state revised. Figure 1.4 Pin Assignment P3_5/SCL P3_5/SCL/SSCK, P3_3 P3_3/SSI, P3_4/SDA P3_4/SDA/SCS, P3_7 P3_7/SSO, VSS/AVSS VSS, XIN/P4_6 P4_6/XIN, VCC/AVSS VCC 12pin P1_7/TRAIO/INT1 to 22pin P1_0/KI0/AN8 20pin P1_7/TRAIO/INT1 to 30pin P1_0/KI0/AN8 Table 1.5 Pin Description - Analog Power Supply Input eliminated. - SSU added. Table 1.6 Pin Name Information by Pin Number added. Table 4.1 SFR Information (1) - 0031h: Voltage Detection Register 1 Voltage Detection A Register 1 - 0032h: Voltage Detection Register 1 Voltage Detection A Register 2 01000001b 00100001b (Note 4) - 0036h: "(3), 01000001b (4)" eliminated. - 0038h: Voltage Monitor 0 Control Register (2), VW0C, 00001000b (3), 01000001b (4) added. Table 4.2 SFR Information (2) - 0048h: Timer RD0 Interrupt Control Register, RD0IC, XXXXX000b added. - 0049h: Timer RD Interrupt Control Register, RDIC Timer RD1 Interrupt Control Register, RD1IC - 004Fh: IIC Interrupt Control Register, IIC IIC/SSU Interrupt Control Register, IIC2IC Table 4.5 SFR Information (3) - 0106h: LIN Control Register, LINCR, 00h added. -0107h: LIN Status Register, LINST, 00h added.
4
5, 6
7
8
9 15
16
19
A-1
REVISION HISTORY
R8C/24 Group, R8C/25 Group Datasheet
Description
Rev. 0.10
Date Feb 24, 2005
Page 1 to 3 5, 6 5 to 7 8 9 13, 14 15
Summary Pin type changed: 48-pin(under consideration) 52-pin. Package type revised: 48-pin LQFP(under consideration) PLQP0052JA-A Table 1.5 TCLK added, VREF revised. Table 1.6 revised. Figures 3.1 and 3.2 part number revised. Tabel 4.1 revised: - 000Fh: 000XXXXXb 00011111b - 0023h: FR0 FRA0 - 0024h: FR1 FRA1 - 0025h: FR2 FRA2 - 0031h: Voltage Detection A Register 1, VC1 Voltage Detection Register 1, VCA1 - 0032h: Voltage Detection A Register 2, VC2 Voltage Detection Register 2, VCA2 Tabel 4.3 Register name and the value after reset at 00B8h to 00BFh revised; NOTE2 added. Tabel 4.5 revised: - 0107h: LINSR LINST - 0137h to 013Fh: Register symbol revised Tabel 4.6 revised: - 0140h to 015Fh: Register symbol revised - 0158h, 0159h: Timer RD General Register Timer RD General Register A1 Tables 1.1, 1.2 and 1.5 revised: "main clock" "XIN clock"; "sub clock" "XCIN clock" - 0023h to 0025h: 40MHz On-Chip Oscillator Control Register High-Speed On-Chip Oscillator Control Register Table 1.1 R8C/24 Group Performance, Table 1.2 R8C/25 Group Performance * Serial Interface revised: - Serial Interface: 2 channels Clock synchronous serial I/O, UART - Clock Synchronous Serial Interface: 1 channel I2C bus Interface(1), Clock synchronous serial I/O with chip select Figure 1.1 Block Diagram * UART or Clock Synchronous Serial Interface: "(8 bits x 1 channel)" "(8 bits x 2 channels)" revised * UART (8 bits x 1 channel) deleted Table 1.3 Product Information of R8C/24 Group, Table 1.4 Product Information of R8C/25 Group "Flash Memory Version" "N Version" revised
17 19
20
0.20
Mar 8, 2005
2, 3 8 15
0.30
Sep 01, 2005
2, 3
4
5, 6
A-2
REVISION HISTORY
R8C/24 Group, R8C/25 Group Datasheet
Description
Rev. 0.30
Date Sep 01, 2005
Page 7
Summary Figure 1.4 Pin Assignment * Pin name revised; VSS VSS/AVSS, VCC VCC/AVCC, P1_5/RXD0/(TRAIO)/(INT1) P1_5/RXD0/(TRAIO)/(INT1)(2), P6_6/INT2/(TXD1) P6_6/INT2/TXD1, P6_7/INT3/(RXD1) P6_7/INT3/RXD1, P6_5 P6_5/CLK1 * NOTE2 added Table 1.5 Pin Description * Analog Power Supply Input: line added * INT Interrupt Input: "INT0 Timer RD input pins. INT1 Timer RA input pins." added * Serial Interface: "CLK1" added * "I2C Bus Interface (IIC)" "I2C Bus Interface" * "SSU" "Clock Synchronous Serial I/O with Chip Select" Table 1.6 Pin Name Information by Pin Number revised * Pin Number 10: "VSS" "VSS/AVSS" * Pin Number 12: "VCC" "VCC/AVCC" * Pin Number 27: "INT0" added * Pin Number 28: "(TXD1)" "TXD1" * Pin Number 29: "(RXD1)" "RXD1" * Pin Number 35: "CLK1" added Tabel 4.1 SFR Information(1) revised: * 0012h: X0h 00h * 0013h: XXXXXX00b 00h * 0016h: X0h 00h * 0036h: Voltage Monitor 1 Control Register(2) Voltage Monitor 1 Control Register(5) * 0038h: 00001000b(3), 01000001b(4) 0000X000b(3), 0100X001b(4) * NOTES2, 5: "the voltage monitor 1 reset" added * NOTE3: "voltage monitor 1 reset" "voltage monitor 0 reset" Tabel 4.2 SFR Information(2) revised: * 0048h: RD0IC TRD0IC * 0049h: RD1IC TRD1IC * 004Ah: REIC TREIC * 004Fh: SSU/IIC Interrupt Control Register, IIC2AIC SSU/IIC Interrupt Control Register(2), SSUAIC/IIC2AIC * 0056h: RAIC TRAIC * 0058h: RBIC TRBIC * NOTE2 added Tabel 4.3 SFR Information(3) revised: * 00BCh: 00h 00h/0000X000b Tabel 4.4 SFR Information(4) revised: * 00D6h: 00000XXXb 00h * 00F5h: UART1 Function Select Register, U1SR, XXh added A-3
8
9
15
16
17 18
REVISION HISTORY
R8C/24 Group, R8C/25 Group Datasheet
Description
Rev. 0.30
Date Sep 01, 2005
Page 19
Summary Tabel 4.5 SFR Information(5) revised: * 0118h : Timer RE Second Data Register/Counter Register Timer RE Second Data Register/Counter Data Register Tabel 4.6 SFR Information(6) revised: * 0145h POCR0 TRDPOCR0 * 0146h, 0147h TRDCNT0 TRD0 * 0148h, 0149h GRA0 TRDGRA0 * 014Ah, 014Bh GRB0 TRDGRB0 * 014Ch, 014Dh GRC0 TRDGRC0 * 014Eh, 014Fh GRD0 TRDGRD0 * 0155h POCR1 TRDPOCR1 * 0156h, 0157h TRDCNT1 TRD1 * 0158h, 0159h GRA1 TRDGRA1 * 015Ah, 015Bh GRB1 TRDGRB1 * 015Ch, 015Dh GRC1 TRDGRC1 * 015Eh, 015Fh GRD1 TRDGRD1 Tabel 4.7 SFR Information(7) revised: * 01B5h: 01000101b 1000000Xb * 01B7h: XX000001b 00000001b * FFFFh: (Note 2) added
20
21
22 to 44 5. Electrical Characteristics added 0.40 Jan 24, 2006 all pages * "Preliminary" deleted * Symbol name "TRDMDR" "TRDMR", "SSUAIC" "SSUIC", and "IIC2AIC" "IICIC" revised * Pin name "TCLK" "TRDCLK" revised 2 3 4 Table 1.1 Functions and Specifications for R8C/24 Group revised Table 1.2 Functions and Specifications for R8C/25 Group revised Figure 1.1 Block Diagram; "Peripheral Functions" added, "System Clock Generation" "System Clock Generator" revised Table 1.3 Product Information for R8C/24 Group revised Table 1.4 Product Information for R8C/25 Group revised Figure 1.4 Pin Assignments (Top View) "TCLK" "TRDCLK" revised Table 1.5 Pin Functions "TCLK" "TRDCLK" revised Table 1.6 Pin Name Information by Pin Number; "TCLK" "TRDCLK" revised Figure 2.1 CPU Registers; "Reserved Area" "Reserved Bit" revised 2.8.10 Reserved Area; "Reserved Area" "Reserved bit" revised Figure 3.1 Memory Map of R8C/24 Group; "Program area" "program ROM" revised 3.2 R8C/25 Group, Figure 3.2 Memory Map of R8C/25 Group; "Data area" "data flash", "Program area" "program ROM" revised A-4
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REVISION HISTORY
R8C/24 Group, R8C/25 Group Datasheet
Description
Rev. 0.40
Date Jan 24, 2006
Page 15
Summary Table 4.1 SFR Information(1); 0024h: "TBD" "When shipping" NOTES 3 and 4 revised Table 4.5 SFR Information (5); 0118h: "Timer RE Second Data Register" "Timer RE Second Data Register / Counter Data Register" 0119h: "Timer RE Minute Data Register" "Timer RE Minute Data Register / Compare Data Register" 0138h: "TRDMDR" "TRDMR" 013Bh: "Timer RD Output Master Enable Register" "Timer RD Output Master Enable Register 1" Table 5.1 Absolute Maximum Ratings; "VCC" "VCC/AVCC" revised Table 5.2 Recommended Operating Conditions revised Table 5.3 A/D Converter Characteristics revised Table 5.4 Flash Memory (Program ROM) Electrical Characteristics revised Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical revised Table 5.6 Voltage Detection 0 Circuit Electrical Characteristics revised Table 5.7 Voltage Detection 1 Circuit Electrical Characteristics revised Table 5.8 Voltage Detection 2 Circuit Electrical Characteristics revised Table 5.11 High-speed On-Chip Oscillator Circuit Electrical Characteristics revised Table 5.12 Low-speed On-Chip Oscillator Circuit Electrical Characteristics revised Table 5.13 Power Supply Circuit Timing Characteristics revised Table 5.14 Timing Requirements of Clock Synchronous Serial I/O with Chip Select revised Table 5.15 Timing Requirements of I2C bus Interface NOTE1 revised Table 5.16 Electrical Characteristics (1) [VCC = 5 V] revised Table 5.17 Electrical Characteristics (2) [VCC = 5 V] revised Table 5.18 XIN Input, XCIN Input revised Table 5.20 Serial Interface revised Table 5.22 Electrical Characteristics (3) [VCC = 3 V] revised Table 5.23 Electrical Characteristics (4) [Vcc = 3 V] revised Table 5.24 XIN Input, XCIN Input revised Table 5.26 Serial Interface revised Table 5.28 Electrical Characteristics (5) [VCC = 2.2 V] revised Table 5.29 Electrical Characteristics (6) [Vcc = 2.2 V] revised Table 5.30 XIN Input, XCIN Input revised Table 5.31 TRAIO Input, INT1 Input revised Table 5.32 Serial Interface revised Table 5.33 External Interrupt INTi (i = 0, 2, 3) Input A-5
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REVISION HISTORY
R8C/24 Group, R8C/25 Group Datasheet
Description
Rev. 0.40 1.00
Date Jan 24, 2006 May 31, 2006
Page 46
Summary Package Dimensions; "TBD" "PLQP0052JA-A (52P6A-A)" added 1. Overview; "data flash ROM" "data flash" revised Table 1.2 Functions and Specifications for R8C/25 Group revised Figure 1.1 Block Diagram; "System clock generator" "System clock generation circuit" revised Table 1.3 Product Information for R8C/24 Group and Table 1.4 Product Information for R8C/25 Group; A part of (D) mark is deleted. Table 1.6 Pin Name Information by Pin Number NOTE1 added Table 4.1 SFR Information(1); 001Ch: "00h" "00h, 10000000b" revised 0029h: High-Speed On-Chip Oscillator Control Register 4 FRA4 When shipping added 002Bh: High-Speed On-Chip Oscillator Control Register 6 FRA6 When shipping added NOTE6 added Table 4.5 SFR Information(5); 0118h: Timer RE Second Data Register / Counter Data Register, 0119h: Timer RE Minute Data Register / Compare Data Register register name revised Table 4.6 SFR Information(6); 0143h: "11000000b" "11100000b" revised Table 5.2 Recommended Operating Conditions revised
Table 5.4 Flash Memory (Program ROM) Electrical Characteristics revised
all pages "Under development" deleted 1 3 4 5 to 6 9 15
19
20 22 24 25 26 27
Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics revised Figure 5.2 Time delay until Suspend title revised
Table 5.9 Voltage Monitor 0 Reset Electrical Characteristics Table 5.9 Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics revised Table 5.10 Power-on Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 0 Reset) deleted Figure 5.3 Power-on Reset Circuit Electrical Characteristics revised
28
Table 5.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics revised Table 5.11 Low-speed On-Chip Oscillator Circuit Electrical Characteristics revised Table 5.16 Electrical Characteristics (2) [Vcc = 5 V] revised Table 5.22 Electrical Characteristics (4) [Vcc = 3 V] revised Table 5.28 Electrical Characteristics (6) [Vcc = 2.2 V] revised Package Dimensions; "The latest package ... Renesas Technology website." added
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A-6
REVISION HISTORY
R8C/24 Group, R8C/25 Group Datasheet
Description
Rev. 2.00
Date Jul 14, 2006
Page 1 2, 3
Summary 1. Overview; "... or a 64-pin molded-plastic FLGA." added Table 1.1 Functions and Specifications for R8C/24 Group, Table 1.2 Functions and Specifications for R8C/25 Group; Package: "64-pin molded-plastic FLGA" added Table 1.3 Product Information for R8C/24 Group, Figure 1.2 Type Number, Memory Size, and Package of R8C/24 Group revised Table 1.4 Product Information for R8C/25 Group, Figure 1.3 Type Number, Memory Size, and Package of R8C/25 Group revised Figure 1.4 PLQP0052JA-A Package Pin Assignments (Top View); NOTE3 revised Figure 1.5 PTLG0064JA-A Package Pin Assignments added Figure 3.1 Memory Map of R8C/24 Group revised Figure 3.2 Memory Map of R8C/25 Group revised Table 5.1 Absolute Maximum Ratings; NOTE1 added Package Dimensions; "PTLG0064JA-A (64F0G)" added
all pages "PTLG0064JA-A (64F0G)" package added
5 6 7 8 14 15 23 47 3.00 Feb 29, 2008
all pages Y version added Factory programming product added 2, 3 5, 7 6, 8 16, 17 18 26 32 Table 1.1, Table 1.2 Clock; "Real-time clock (timer RE)" added Table 1.3, Table 1.4 revised Figure 1.2, Figure 1.3; ROM number "XXX" added Figure 3.1, Figure 3.2; "Expanded area" deleted Table 4.1 revised Table 5.2 NOTE2 revised Table 5.10; revised, NOTE4 added Table 5.11; Oscillation stability time: Condition "VCC = 5.0 V, Topr = 25C" deleted Table 5.15; IIH, IIL, RPULLUP Condition: "Vcc = 5V" added Table 5.16; Condition: High-speed on-chip oscillator mode revised Table 5.17 added Figure 5.8 revised Table 5.22; IIH, IIL, RPULLUP Condition: "Vcc = 3V" added Table 5.23; Condition "Increase during A/D converter operation" added Figure 5.12 revised Table 5.29; Condition "Increase during A/D converter operation" added Figure 5.16 revised
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A-7
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Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. 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Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. 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